Conventionally, a semiconductor device in which a plurality of semiconductor substrates having an element layer is laminated is used.
In order to increase speed, reduce power consumption, etc., of an electronic device, a three-dimensional packaging technique for laminating a plurality of semiconductor substrates having an element layer for accommodating the semiconductor substrates in one package has been proposed.
In the three-dimensional packaging technique, an electrode that penetrates through a semiconductor substrate is used in order to electrically connect semiconductor substrates to be laminated.
FIG. 1 is a diagram depicting a conventional semiconductor device.
A semiconductor device 101 is formed by laminating a first semiconductor substrate 11 having a first element layer 12 and a second semiconductor substrate 31 having a second element layer 32. The first element layer 12 and the second element layer 32 are electrically connected via through electrodes 120a and 120b penetrating through the first semiconductor substrate 11, bumps 42a and 42b, etc.
The first semiconductor substrate 11 has a first surface 11a on which the first element layer 12 is formed and a second surface 11b on the opposite side of the first surface 11a. The through electrodes 120a and 120b penetrate through the first semiconductor substrate 11 from the first surface 11a toward the second surface 11b and part thereof protrudes from the second surface 11b. The side surfaces of the through electrodes 120a and 120b are coated with barrier layers 23a and 23b and electrode insulation layers 24a and 24b. 
On the second surface 11b of the first semiconductor substrate 11, a first insulation layer 114 is laminated so as to embed the side surfaces of the through electrodes 120a and 120b. The first insulation layer 114 has openings 117a and 117b through which the through electrodes 120a and 120b are exposed. End surfaces 121a and 121b on the side of the second surface 11b of the through electrodes 120a and 120b are exposed through the openings 117a and 117b. 
The thickness of the first insulation layer 114 is less than the length of the portions of the through electrodes 120a and 120 protruding from the second surface 11b. The thickness of the portion of the first insulation layer 114 between the through electrode 120a and the through electrode 120b is less than that of the portions covering the side surfaces of the through electrodes 120a and 120b. 
On the first element layer 12 of the first semiconductor substrate 11, a first wire layer 13 is laminated. To the end parts on the side of the first surface 11a in the lengthwise direction of the through electrodes 120a and 120b, contacts 22a and 22b arranged within the first wire layer 13 are connected. The through electrodes 120a and 120b are electrically connected with the first element layer 12 via the contacts 22a and 22b. On the contacts 22a and 22b, bumps, not depicted, are arranged.
On the second element layer 32 of the second semiconductor substrate 31, a second wire layer 33 is laminated. On the second wire layer 33, a second insulation layer 34 is laminated.
Within the second wire layer 33, contacts 40a and 40b electrically connected to the second element layer 32 are arranged. On the contacts 40a and 40b, pads 41a and 41b are arranged. On the pads 41a and 41b, the bumps 42a and 42b are arranged.
Part of the pads 41a and 41b and the bumps 42a and 42b is embedded within the second insulation layer 34.
The end surfaces 121a and 121b on the side of the second surface 11b of the through electrodes 120a and 120b are in contact with the bumps 42a and 42b. 
Between the first insulation layer 114 and the second insulation layer 34, a filler layer 15 is filled in so as to embed the bumps 42a and 42b. 
The first element layer 12 on the first semiconductor substrate 11 and the second element layer 32 on the second semiconductor substrate 31 are electrically connected via the contacts 22a and 22b, the through electrodes 120a and 120b, the bumps 42a and 42b, the pads 41a and 41b, and the contacts 40a and 40b. 
Japanese Laid-open Patent Publication No. 2005-12024
As described above, the through electrode 120a protrudes from the second surface 11b and the length of the protruding portion is greater than the thickness of the first insulation layer 114. Consequently, when the bump 42a and the through electrode 120a are joined, there is a case where a part 42c of the molten bump 42a flows out to the lateral side of the through electrode 120a. If the electric conductor forming the bump 42a extends onto the first insulation layer 114, there is a possibility that a current leak path is formed.
As described above, with the conventional three-dimensional packaging technique of a semiconductor device, there is a possibility that a failure may occur in joining of the bump and the through electrode.